Energy efficiency of FPGAs and programmable processors for matrix multiplication

An Algorithm Designer's Workbench for Platform FPGA's

Growing gate density, availability of embedded multipliers and memory, and integration of traditional processors are some of the key advantages of Platform FPGAs. Such FPGAs are attractive for implementing compute intensive signal processing kernels used in wired as well as wireless mobile devices. However, algorithm design using Platform FPGAs, with energy dissipation as an additional performa...

Energy-Efficient Matrix Multiplication on FPGAs

Energy-Efficient Design of Kernel Applications for FPGAs Through Domain-Specific Modeling

Because of their high performance and flexibility, FPGAs are an attractive option for use in embedded systems, where both high performance and low energy consumption are important. Therefore, it is important to create FPGA designs that are not only high performance but also low energy. The flexibility of FPGAs facilitates their high performance, but also makes it difficult to design for them. T...

Sparse Matrix-Vector Multiplication on FPGAs

Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientic and engineering applications. The poor data locality of sparse matrices signicantly reduces the performance of SpMXV on general-purpose processors, which rely heavily on the cache hierarchy to achieve high performance. The abundant hardware resources on current FPGAs provide new opportunities to...

Hera: a Reconfigurable and Mixed-mode Parallel Computing Engine on Platform Fpgas*

The high price, long design and development cycles, programming difficulty and high maintenance cost of supercomputers limit their range of potential applications. Recent advances in Field-Programmable Gate Arrays (FPGAs) have made feasible the development of highperformance and programmable parallel systems on a programmable chip (PSOPC). PSOPC’s yield highperformance at low cost for many para...